Integrated circuits are produced by means of a fabrication process which converts a circuit design into an operable device. The fabrication process consists of a sequence of steps which transforms a substrate of semiconductor material, typically silicon, into a device with multiple layers, each having a specific pattern of structures and interconnections. A finished integrated circuit is usually comprised of a multitude of smaller devices which are electrically connected in a desired manner.
In order for an integrated circuit to properly operate, it is necessary that the component devices initially be electrically isolated from each other. The devices can then be connected by means of standard interconnection techniques. Isolation techniques are thus a critical part of the fabrication process, because without them, properly functioning complex integrated circuits could not be constructed.
The importance of device isolation to the fabrication of integrated circuits has lead to the development of a variety of processes which are designed to achieve that goal. A variety of isolation processes are required because different types of integrated circuits (e.g., NMOS, CMOS, bipolar) have differing electrical and structural characteristics, and this can affect the type of structure required for effective isolation. The isolation techniques vary in such attributes as minimum isolation spacing (the minimum separation required to isolate structures), planarity of the final surface (which impacts the ease with which later fabrication steps can be carded out), complexity of the isolation process, and the density of defects created during the process.
One of the most common isolation methods involves the formation of field oxide regions. One of the most basic methods of forming field oxide regions is termed the direct isolation technique. This involves the formation of an oxide layer in the inactive or field regions of the substrate on which the devices are fabricated. The oxide is grown as a continuous film which is selectively removed from the active regions by means of photolithographic techniques. This isolation process is used for MOS integrated circuits and is designed to prevent the formation of channels in the field oxide regions between individual devices, where such channels would serve to electrically connect the devices.
In the direct isolation process the entire isolation oxide is grown above the surface of the silicon substrate. This produces a highly non-planar surface after the oxide is removed from the active regions. For this reason, several variants of the direct isolation technique have been developed. These variants include the fully recessed isolation oxide process (which involves etching trenches into the substrate to a sufficient depth so that the final oxide layer is level with the surface of the substrate) and the semi-recessed local oxidation of silicon (LOCOS) isolation process.
One problem with the use of field oxide isolation methods is the formation of "bird's beak" or "bird's head" structures. The "bird's beak" structure results from lateral oxidation under the nitride masks used in the standard LOCOS procedure. The "bird's head" formation results from lateral oxidation under the nitride masks used in recessed or etch back LOCOS procedures. The walls of the recessed portions of the substrate adjacent to the nitride masks, which are a feature of these procedures, greatly facilitate the lateral oxidation. These formations ("bird's beak" and "bird's head") encroach upon the active device area, thereby requiring greater isolation distances between active device regions to compensate for this encroachment and resulting in a considerable reduction of the packing density of the devices. Various methods have been proposed to overcome the limits on packing density imposed by the use of field oxide isolation methods. One such method, referred to as "BOX", has been proposed by Kurosawa et al. in "A New Bird's-Beak Free Field Isolation Technology for VLSI Devices", International Electron Devices Meeting, Dig. Tech. Paper, pp. 384-387 (1981). The name "BOX" has been given to this method because it involves burying oxide into etched grooves formed in silicon substrates. According to this method, the silicon substrate is etched in the field region using reactive ion etching (RIE), leaving a layer of aluminum coveting the active device areas. Silicon dioxide (SiO.sub.2) is then plasma deposited over the entire substrate. The silicon dioxide fills up the portion of the substrate previously etched away and also covers the aluminum layer.
The plasma deposited silicon dioxide is then subjected to a lift-off technique using a buffered HF solution. This leaves V-shaped grooves in the periphery of the active region. The silicon dioxide on top of the aluminum mask is lifted off by an etch step. The remaining V-shaped grooves are then buried under silicon dioxide in a second step. This is accomplished by chemical vapor deposition (CVD) of silicon dioxide, followed by a planarization step using a spin-coated resist. The resist and silicon dioxide layers are simultaneously etched by RIE. The oxide surfaces are then smoothed and any oxide remaining on the active device region is removed by solution etching.
A drawback to the use of the BOX method is that it is very complex and cannot always be performed efficiently and reliably. First of all, a two step oxide burying technique is needed, which is more time consuming than a single oxide deposition step. Furthermore, resist planarization and resist etch back steps are involved, which are difficult to control to close tolerances in a manufacturing environment. In addition, resist planarization and etch-back techniques are not as effective and are difficult to properly implement for devices having large active regions, i.e., global planarity is difficult to achieve.
Another type of isolation process which has been developed to separate individual active device regions on a semiconductor substrate is termed the "trench etch and refill" technique. This method is based on the fabrication of shallow or deep trench structures in the substrate, with the trenches then being filled with an insulator. The technique has been used in the fabrication of several types of devices: the replacement of the LOCOS (local oxidation of silicon) technique for devices having the same channel type within the same tub in CMOS devices, for isolation of bipolar devices, for isolation of n-channel from p-channel devices and to prevent latchup in CMOS, for use as trench-capacitor structures in dynamic random access memory devices (DRAMs), and for use in load resistor structures in static random access memory devices (SRAMS).
An example of a trench isolation method is disclosed in a publication by Rung et al. entitled, "Deep Trench Isolated CMOS Devices", International Electron Devices Meeting, Digest Technical Paper, pp. 237-240 (1982). According to this method, trenches are formed by RIE and are then filled with silicon dioxide or poly-silicon which are deposited by using low pressure chemical vapor deposition (LPCVD). Once the trenches are filled, a critical etch back step must be accomplished using end point detection. After the etch back step, a capping oxidation step is performed using a nitride layer as an oxidation mask. This isolation method is somewhat complicated as it uses a trench masking oxide layer to define the trench locations and another oxide layer for the purpose of forming the field oxide regions.
Yet another isolation method is disclosed by Katsumata et al. in "Sub-20 ps ECL Bipolar Technology with High Breakdown Voltage", ESSDERC (September 1993). In this paper, the authors disclose a shallow and deep trench isolation method using Low-Temperature Oxide Filling. According to this method, shallow and deep trenches are etched and then filled by a low-temperature, liquid oxide deposition step. A photoresist mask is then formed over the field areas and the exposed portions of the oxide layer are etched. Next, a second step of liquid oxide deposition is performed, followed by another etch back step. Hence, this process uses a critical alignment step and two liquid oxide deposition and etch back steps, all of which are not easily translated to a manufacturing environment. The above-mentioned problems with respect to forming isolation regions around large active regions apply to this technique as well.
A problem common to many types of isolation processes is the difficulty in achieving a highly planarized final surface or intermediate dielectric layer. A highly planarized surface is important because it allows full utilization of the optimal resolution of modem lithography tools and thus maximizes the packing density of devices. A planar surface assists with subsequent fabrication steps by providing a uniform surface on which other materials can be deposited or on which other processes can operate. Thus, the uniform filling of trenches or spaces and the formation of a highly planar surface is important to the formation of isolation regions during the fabrication of integrated circuits.
What is desired is an isolation method which can produce a highly planar final surface and which is not susceptible to many of the problems associated with existing isolation techniques, such as the difficulty in achieving global planarity and the encroachment of isolation regions into active regions of the device.